GENERATION OF 1-BIT FULL ADDER IN CMOS AND TG LOGIC DESIGN FOR LOW POWER APPLICATION

This paper presents the comparative performance analysis of a 1-bit full adder in two different logic styles CMOS & TG. In this work, the foremost concentration is to lower power dissipation & delay by using the technology scaling approach and developing the circuit to operate at low voltage levels. The circuit interaction is made possible for designing more consistent functional architectures at the minimum power supply of 0.45-1.8v. In the conventional method, two half adders are designed to construct a full adder using an XOR-AND gate to generate a SUM and CARRY( 1-bit) with 28 transistors in static CMOS logic, such a high transistor count to generate 1-bit impliesrequiring more transistors to generate 4,8,16,32 bit. To minimize the transistor count another logic style called transmission gate (TG) is introduced to design such complex designs in an easier manner. The simulation results of 1-bit full adder CMOS, TG logic are taken from CADENCE Virtuoso in 180, 90 & 45nm technology and the parametric analysis proved better results for TG. This paper presents the comparative performance analysis of a 1-bit full adder in two different logic styles CMOS & TG. In this work, the maximum concentration is to lower power dissipation & delay by using the technology scaling approach and developing the circuit to operate at low voltage levels. The circuit interaction is made possible for designing more consistent functional architectures at the minimum power supply of 0.45-1.8v. In the conventional method, two half adders are intended to construct a full adder using an XOR - AND gate to generate a SUM and CARRY (1-bit) with 28 transistors instatic CMOS logic, such a high transistor count to generate 1-bit implies requiring more transistors to generate 4,8,16,32 bit. To minimize the transistor count another logic style called transmission gate (TG) is introduced to design such complex designs in a more accessible manner. The simulation results of 1-bit full adder CMOS, TG logic are taken from CADENCE Virtuoso in 180, 90 & 45nm technology and the parametric analysis proved better results for TG.